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pentium ? /ii, 6x86, k6 clock synt hesizer/driver for desktop / mobile pcs with intel ? 82430tx and 2 dimms or 3 so-dimms cy2277a rev 1.0, november 25, 2006 page 1 of 18 2200 laurelwood road, santa clara, ca 95054 tel:(4 08) 855-0555 fax:(408) 855-05 50 www.spectralinear.com 1cy2277a features ? mixed 2.5v and 3.3v operation ? complete clock solution to meet requirements of pentium ? , pentium ? ii, 6x86, or k6 motherboards ? four cpu clocks at 2.5v or 3.3v ? up to eight 3.3v sdram clocks ? seven 3.3v synchronous pci clocks, one free running ? two 3.3v usb/io clocks at 48 or 24 mhz, selectable by serial interface ? one 2.5v ioapic clock at 14.318 mhz ? two 3.3v ref. clocks at 14.318 mhz ? factory-eprom programmable cpu, pci, and usb/io clock frequencies for custom configuration ? factory-eprom programmabl e output drive and slew rate for emi customization ? mode enable pin for cpu_stop and pci_stop ? smbus serial configuration interface ? available in space-saving 48-pin ssop and tssop packages. functional description the cy2277a is a clock synthe sizer/driver for pentium, pentium ii, 6x86, and k6 portable pcs designed with the intel ? 82430tx or similar chipsets. there are three available options as shown in the selector guide the cy2277a outputs four cpu cloc ks at 2.5v or 3.3v with up to nine selectable frequencies. there are up to eight 3.3v sdram clocks and seven pci clocks, running at one half the cpu clock frequency. one of the pci clocks is free-running. additionally, the part outputs two 3.3v usb/io clocks at 48 mhz or 24 mhz, one 2.5v ioapic clock at 14.318 mhz, and two 3.3v reference clocks at 14.318 mhz. the cpu, pci, usb, and io clock frequencies are factory-eprom program- mable for easy customization with fast turnaround times. the cy2277a has power-down, cpu stop and pci stop pins for power management contro l. the cpu stop and pci stop are controlled by the mode pi n. they are multiplexed with sdram clock outputs, and are selected when the mode pin is driven low. additionally, t hese inputs are synchronized on-chip, enabling glitch-free transitions. when the cpu_stop input is asserted, the cpu outputs are driven low. when the pci_stop input is asserted, the pci outputs (except the free-running pci clock) are driven low. finally, when the pwr_dwn pin is asserted, the reference oscillator and plls are shut down, and all outputs are driven low. the cy2277a outputs are designed for low emi emission. controlled rise and fall times, unique output driver circuits and factory-eprom programmable output drive and slew-rate enable optimal configurations for emi control. . eprom pin configuration logic block diagram xtalout xtalin ioapic (14.318 mhz) 14.318 mhz osc. sdram[0?5] sel sdram7/pci_stop v ddq2 cpu pll mode sys pll /2 delay 1 2 3 4 5 6 7 8 9 10 11 12 33 32 31 30 29 25 26 27 28 36 35 ref1 34 top view 13 14 15 16 17 18 19 20 21 22 23 24 45 44 43 42 41 37 38 39 40 48 47 46 cy2277a-1,-1m,-3,-7m,-12,-12m,-12i ref0 v ss xtalin xtalout mode v ddq3 pciclk_f pciclk0 v ss pciclk1 pciclk2 pciclk3 pciclk4 v ddq3 pciclk5 v ss sel sdata sclk v ddq3 usbclk/ioclk usbclk/ioclk v ss av dd pwr_sel v ddq2 ioapic pwr_dwn v ss cpuclk0 cpuclk1 v ddcpu cpuclk2 cpuclk3 v ss sdram0 sdram1 v ddq3 sdram2 sdram3 v ss sdram4 sdram5 v ddq3 sdram6/cpu_stop sdram7/pci_stop av dd sclk sdata ref [0?1] (14.318) cpuclk[0?3] v ddcpu sdram6/cpu_stop pci[0?5] pciclk_f usbclk/ioclk[0:1] stop stop interface control logic serial logic logic divide and mux logic pwr_dwn
cy2277a rev 1.0, november 25, 2006 page 2 of 18 pin summary name pins description v ddq3 7, 15, 21, 28, 34 3.3v digital voltage supply v ddq2 46 ioapic digital voltage supply, 2.5v v ddcpu 40 cpu digital voltage supply, 2.5v or 3.3v av dd 25, 48 3.3v analog voltage supply v ss 3, 10, 17, 24, 31, 37, 43 ground xtalin [1] 4 reference crystal input xtalout [1] 5 reference crystal feedback mode 6 mode select input, enable s power management features sel 18 select input to enable 66.66 mhz or 60 mhz cpu clock (see function tables.) sdata 19 smbus serial data input for serial configuration port sclk 20 smbus serial clock input for serial configuration port pwr_dwn 44 active low control input to put osc., plls, and outputs in power down state pwr_sel 47 power select input, indicates whether v ddcpu is at 2.5v or 3.3v high = 3.3v, low=2.5v (internal pull-up to v dd ) sdram7/pci_stop 26 sdram clock output. also, active low control input to stop pci clocks, enabled when mode is low sdram6/cpu_stop 27 sdram clock output. also, active low control input to stop cpu clocks, enabled when mode is low sdram[0:5] 36, 35, 33, 32, 30, 29 sdram clock outputs, have same frequency as cpu clocks cpuclk[0:3] 42, 41, 39, 38 cpu clock outputs pciclk[0:5] 9, 11, 12, 13, 14, 16 pci clock outputs pciclk_f 8 pci clock outpu t, free-running ioapic 45 ioapic clock output ref[0:1] 1, 2 reference clock outputs, 14.318 mhz. ref0 drives 45 pf load usbclk/ioclk 22, 23 usb or io clock outputs, frequency selected by serial word note: 1. for best accuracy, use a parallel-resonant crystal, c load = 18 pf. table 1. cy2277a selector guide clock outputs -1/-1m -3 -7m -12/-12m/-12i cpu (60, 66.6 mhz) 4 -- 4 4 cpu (33.3, 66.6 mhz) -- 4 -- -- cpu (smbus selectable) -- -- -- -- pci (cpu/2) 7 [2] 7 [2] 7 [2] 7 [2] sdram 6/8 6/8 6/8 6/8 usb/io (48 or 24 mhz) 2 2 2 2 ioapic (14.318 mhz) 1 1 1 1 ref (14.318 mhz) 2 2 2 2 cpu-pci delay 1?6 ns 1?6 ns <1 ns 1?4 ns note: 2. one free-running pci clock
cy2277a rev 1.0, november 25, 2006 page 3 of 18 cpu and pci clock driver strengths ? matched impedances on both rising and falling edges on the output drivers ? output impedance: 25 (typical) measured at 1.5v notes: 3. on power-up, the default frequency on these outputs is 48 mhz. 4. meets intel usb clock requirements. 5. tclk supplied on the xtalin, pin 4. function table (-3) sel xtalin cpuclk[0:3] sdram[0:7] pciclk[0:5] pciclk_f ref[0:1] ioapic usbclk / ioclk [3] 0 14.318 mhz 33.33 mhz 16.67 mhz 14.318 mhz 48.0 mhz / 24.0 mhz 1 14.318 mhz 66.67 mhz 33.33 mhz 14.318 mhz 48.0 mhz / 24.0 mhz function table (-1, -1m, -7m, -12, -12m, -12i) sel xtalin cpuclk[0:3] sdram[0:7] pciclk[0:5] pciclk_f ref[0:1] ioapic usbclk / ioclk [3] 0 14.318 mhz 60.0 mhz 30.0 mhz 14.318 mhz 48.0 mhz / 24.0 mhz 1 14.318 mhz 66.67 mhz 33.33 mhz 14.318 mhz 48.0 mhz / 24.0 mhz actual clock frequency values (-1, -1m, -3, -7m, -12, -12m, -12i) clock output target frequency (mhz) actual frequency (mhz) ppm cpuclk, sdram 66.67 66.654 ?195 cpuclk, sdram 60.0 60.0 0 usbclk [4] 48.0 48.008 167 ioclk 24.0 24.004 167 power management logic cpu_stop pci_stop pwr_dwn cpuclk pciclk pciclk_f other clocks osc. plls x x 0 low low stopped stopped off off 0 0 1 low low running running running running 0 1 1 low 33/30 mhz running running running running 1 0 1 66/60 mhz low running running running running 1 1 1 66/60 mhz 33/30 mhz running running running running select functions functional description outputs cpu pci, pci_f sdram ref ioapic ioclk usbclk three-state hi-z hi-z hi-z hi-z hi-z hi-z hi-z test mode tclk/2 [5] tclk/4 tclk/2 tclk tclk tclk/4 tclk/2
cy2277a rev 1.0, november 25, 2006 page 4 of 18 serial configuration map ? the serial bits will be read by the clock driver in the following order: byte 0 - bits 7, 6, 5, 4, 3, 2, 1, 0 ? byte 1 - bits 7, 6, 5, 4, 3, 2, 1, 0 ? byte n - bits 7, 6, 5, 4, 3, 2, 1, 0 ? reserved and unused bits should be programmed to ?0?. ? smbus address for the cy2277a is: table 2. a6 a5 a4 a3 a2 a1 a0 r/w 1 1 0 1 0 0 1 ---- byte 0: functional and frequency select clock register (1 = enable, 0 = disable) bit pin # description bit 7 -- (reserved) drive to ?0? bit 6 -- (reserved) drive to ?0? on -1, -1m, -3, -7m, -12, -12m, -12i bit 5 -- (reserved) drive to ?0? on -1, -1m, -3, -7m, -12, -12m, -12i bit 4 -- (reserved) drive to ?0? on -1, -1m, -3, -7m, -12, -12m, -12i bit 3 23 48/24 mhz (frequency select) 1 = 48 mhz (default), 0 = 24 mhz bit 2 22 48/24 mhz (frequency select) 1 = 48 mhz (default), 0 = 24 mhz bit 1 bit 0 -- bit 1 1 1 0 0 bit 0 1 - three-state (see table below) 0 - n/a 1 - test mode (see table below) 0 - normal operation byte 0: functional and frequency select clock register (1 = enable, 0 = disable)
cy2277a rev 1.0, november 25, 2006 page 5 of 18 byte 1: cpu, 24/48 mhz active/inactive register (1 = active, 0 = inactive), default = active bit pin # description bit 7 23 48/24 mhz (act ive/inactive) bit 6 22 48/24 mhz (act ive/inactive) bit 5 -- (reserved) drive to ?0? bit 4 n/a not used, drive 0 bit 3 38 cpuclk3 (active/inactive) bit 2 39 cpuclk2 (active/inactive) bit 1 41 cpuclk1 (active/inactive) bit 0 42 cpuclk0 (active/inactive) byte 3: sdram active/inactive register (1 = active, 0 = inactive), default = active bit pin # description bit 7 26 sdram7 (active/inactive) bit 6 27 sdram6 (active/inactive) bit 5 29 sdram5 (active/inactive) bit 4 30 sdram4 (active/inactive) bit 3 32 sdram3 (active/inactive) bit 2 33 sdram2 (active/inactive) bit 1 35 sdram1 (active/inactive) bit 0 36 sdram0 (active/inactive) byte 5: peripheral active/inactive register (1 = active, 0 = inactive), default = active bit pin # description bit 7 -- (reserved) drive to ?0? bit 6 -- (reserved) drive to ?0? bit 5 -- (reserved) drive to ?0? bit 4 45 ioapic (active/inactive) bit 3 -- (reserved) drive to ?0? bit 2 -- (reserved) drive to ?0? bit 1 1 ref1 (active/inactive) bit 0 2 ref0 (active/inactive) byte 2: pci active/inactive register (1 = active, 0 = inactive), default = active bit pin # description bit 7 -- (reserved) drive to ?0? bit 6 8 pciclk_f (active/inactive) bit 5 16 pciclk5 (active/inactive) bit 4 14 pciclk4 (active/inactive) bit 3 13 pciclk3 (active/inactive) bit 2 12 pciclk2 (active/inactive) bit 1 11 pciclk1 (active/inactive) bit 0 9 pciclk0 (active/inactive) byte 4: sdram active/inactive register (1 = active, 0 = inactive), default = active bit pin # description bit 7 n/a not used, drive to ?0? bit 6 n/a not used, drive to ?0? bit 5 n/a not used, drive to ?0? bit 4 n/a not used, drive to ?0? bit 3 n/a not used, drive to ?0? bit 2 n/a not used, drive to ?0? bit 1 n/a not used, drive to ?0? bit 0 n/a not used, drive to ?0? byte 6: reserved, for future use
cy2277a rev 1.0, november 25, 2006 page 6 of 18 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) supply voltage ..................................................?0.5 to +7.0v input voltage ............................................ ?0.5v to v dd + 0.5 storage temperature (non-condensing) .... ?65 c to +150 c junction temperature............................................... +150 c package power dissipation........ ...................................... 1w static discharge voltage............................................ >2000v (per mil-std-883, method 3015, like v dd pins tied together) operating conditions [6] parameter description min. max. unit av dd , v ddq3 analog and digital supply voltage 3.135 3.465 v v ddcpu 2.5v cpu supply voltage (-1,-1m, -3, -7m) 2.5v cpu supply voltage (-12, -12m, -12i) 3.3v cpu supply voltage 2.375 2.375 3.135 2.9 2.625 3.465 v v ddq2 2.5v ioapic supply voltage (-1,-1m, -3, -7m) 2.5v ioapic supply voltage (-12, -12m, -12i) 3.3v ioapic supply voltage 2.375 2.375 3.135 2.9 2.625 3.465 v t a operating temperature, commercial 0 70 c t a operating temperature, industrial ?40 85 c c l max. capacitive load on cpuclk, usbclk/ioclk, ref1, ioapic pciclk, sdram ref0 10 30, 20 20 20 30 45 pf f (ref) reference frequency, oscillator nominal value 14.318 14.318 mhz t pu power-up time for all vdd's to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms electrical characteristics (-1, -3, -12) parameter description test conditions min. max. unit v ih high-level input voltage except crystal inputs 2.0 v v il low-level input voltage except crystal inputs 0.8 v v iliic low-level input voltage smbus inputs only 0.7 v v oh high-level output voltage [7] v ddq2 = v ddcpu = 2.375v i oh = 18 ma cpuclk 2.0 v i oh = 18 ma ioapic v ol low-level output voltage [7] v ddq2 = v ddcpu = 2.375v i ol = 29 ma cpuclk 0.4 v i ol = 29 ma ioapic v oh high-level output voltage [7] v ddq3 , av dd , v ddcpu = 3.135v i oh = 32 ma cpuclk 2.4 v i oh = 36 ma sdram i oh = 32 ma pciclk i oh = 26 ma usbclk i oh = 26 ma ioclk i oh = 36 ma ref0 i oh = 26 ma ref1 v ol low-level output voltage [7] v ddq3 , av dd , v ddcpu = 3.135v i ol = 24 ma cpuclk 0.4v v i ol = 29 ma sdram i ol = 26 ma pciclk i ol = 21 ma usbclk i ol = 21 ma ioclk i ol = 29 ma ref0 i ol = 21 ma ref1
cy2277a rev 1.0, november 25, 2006 page 7 of 18 i ih input high current v ih = v dd ?10 +10 a i il input low current v il = 0v, except pwr_sel 10 a i il input low current v il = 0v, pwr_sel only 100 a i oz output leakage current three-state ?10 +10 a i dd power supply current [7, 8] v dd = 3.465v, v in = 0 or v dd , loaded outputs, cpu = 66.67 mhz 250 ma i dd power supply current [7, 8] v dd = 3.465v, v in = 0 or v dd , unloaded outputs 120 ma i dds power-down current current draw in power-down state, pwr_sel = v dd 150 a electrical characteristics (-1, -3, -12) (continued) parameter description test conditions min. max. unit electrical characteristics (-1m, -7m, -12m) parameter description test conditions min. max. unit v ih high-level input voltage except crystal inputs 2.0 v v il low-level input voltage except crystal inputs 0.8 v v iliic low-level input voltage smbus inputs only 0.7 v v oh high-level output voltage [7] v ddq2 = v ddcpu = 2.375v i oh = 12.6 ma cpuclk 1.75 v i oh = 16.7ma ioapic v ol low-level output voltage [7] v ddq2 = v ddcpu = 2.375v i ol = 18.2 ma cpuclk 0.4 v i ol = 23.1 ma ioapic v oh high-level output voltage [7] v ddq3 , av dd , v ddcpu = 3.135v i oh = 32.2 ma sdram 2.4 v i oh = 32.2 ma pciclk i oh = 32.2 ma usbclk i oh = 32.2 ma ioclk i oh = 32.2 ma ref0 i oh = 32.2 ma ref1 v ol low-level output voltage [7] v ddq3 , av dd , v ddcpu = 3.135v i ol = 23.8 ma sdram 0.8v v i ol = 23.8 ma pciclk i ol = 23.8 ma usbclk i ol = 23.8 ma ioclk i ol = 23.8 ma ref0 i ol = 23.8 ma ref1 i ih input high current v ih = v dd ?10 +10 a i il input low current v il = 0v, except pwr_sel 10 a i il input low current v il = 0v, pwr_sel only 100 a i oz output leakage current three-state ?10 +10 a i dd power supply current [7, 8] v dd = 3.465v, v in = 0 or v dd , loaded outputs, cpu = 66.67 mhz 250 ma i dd power supply current [7, 8] v dd = 3.465v, v in = 0 or v dd , unloaded outputs 120 ma i dds power-down current current draw in power-down state, pwr_sel = v dd 150 a notes: 6. electrical parameters are guaranteed with these operating conditions. 7. guaranteed by design and characteriza tion. not 100% tested in production. 8. power supply current will vary with number of outputs which are running.
cy2277a rev 1.0, november 25, 2006 page 8 of 18 electrical characteristics (-12i) parameter description test conditions min. max. unit v ih high-level input voltage e xcept crystal inputs 2.0 v v il low-level input voltage e xcept crystal inputs 0.8 v v iliic low-level input voltage smbus inputs only 0.7 v v oh high-level output voltage [7] v ddq2 = v ddcpu = 2.375v i oh = 18 ma cpuclk 1.75 v i oh = 18 ma ioapic v ol low-level output voltage [7] v ddq2 = v ddcpu = 2.375v i ol = 29 ma cpuclk 0.4 v i ol = 29 ma ioapic v oh high-level output voltage [7] v ddq3 , av dd , v ddcpu = 3.135v i oh = 32 ma cpuclk 2.4 v i oh = 36 ma sdram i oh = 32 ma pciclk i oh = 26 ma usbclk i oh = 26 ma ioclk i oh = 36 ma ref0 i oh = 26 ma ref1 v ol low-level output voltage [7] v ddq3 , av dd , v ddcpu = 3.135v i oh = 24ma cpuclk 0.8v v i oh = 29 ma sdram i oh = 26 ma pciclk i ol = 21 ma usbclk i oh = 21 ma ioclk i ol = 29ma ref0 i oh = 21 ma ref1 i ih input high current v ih = v dd ?20 +20 a i il input low current v il = 0v, except pwr_sel 10 a i il input low current v il = 0v, pwr_sel only 100 a i oz output leakage current three-state ?10 +10 a i dd power supply current [7, 8] v dd = 3.465v, v in = 0 or v dd , loaded outputs, cpu = 66.67 mhz 250 ma i dd power supply current [7, 8] v dd = 3.465v, v in = 0 or v dd , unloaded outputs 120 ma i dds power-down current current draw in power-down state, pwr_sel = v dd 150 a
cy2277a rev 1.0, november 25, 2006 page 9 of 18 switching characteristics (-1, -3) [9, 10, 11] parameter output description test conditions min. typ. max. unit t 1 cpuclk sdram usbclk ioclk ref [0,1] ioapic output duty cycle [12] t 1 = t 1a t 1b 45 50 55 % t 1 pci output duty cycle [12] t 1 = t 1a t 1b 40 50 55 % t 2 cpuclk, ioapic cpu and ioapic clock rising and falling edge rate between 0.4v and 2.0v, v ddcpu = 2.5v between 0.4v and 2.4v, v ddcpu = 3.3v cpu clocks at 66.66 mhz 0.75 0.75 4.0 4.0 v/ns t 2 pci pci clock rising and falling edge rate between 0.4v and 2.4v, v ddcpu = 3.3v 0.75 4.0 v/ns t 2 usbclk, ioclk, ref0 usb, i/o, ref0 clock rising and falling edge rate between 0.4v and 2.4v 0.8 4.0 v/ns t 2 sdram sdram rising and falling edge rate between 0.4v and 2.4v sdram clocks at 66.66 mhz 1.0 4.0 v/ns t 2 ref1 ref1 rising and falling edge rate between 0.4v and 2.4v 0.5 2.0 v/ns t 3 cpuclk cpu clock rise time between 0.4v and 2.0v, v ddcpu = 2.5v between 0.4v and 2.4v, v ddcpu = 3.3v 0.4 0.5 2.13 2.0 ns t 3 usbclk, ioclk usb clock and i/o clock rise time between 0.4v and 2.4v 2.5 ns t 4 cpuclk cpu clock fall time between 2.0v and 0.4v, v ddcpu = 2.5v between 2.4v and 0.4v, v ddcpu = 3.3v 0.4 0.5 2.13 2.0 ns t 4 usbclk, ioclk usb clock and i/o clock fall time between 2.4v and 0.4v 2.5 ns t 5 cpuclk cpu-cpu clock skew measured at 1.25v, v ddcpu = 2.5v 100 400 ps t 6 cpuclk, pciclk cpu-pci clock skew (-1, -3) measured at 1.25v fo r 2.5v clocks, and at 1.5v for 3.3v clocks 1.0 2.0 6.0 ns t 7 cpuclk, sdram cpu-sdram clock skew measured at 1.25v fo r 2.5v clocks, and at 1.5v for 3.3v clocks, v ddcpu = 2.5v 775 ps t 8 cpuclk cycle-cycle clock jitter measured at 1.25v for 2.5v clocks and at 1.5v for 3.3v clocks 450 ps t 8 sdram cycle-cycle clock jitter measured at 1.5v for 3.3v clocks 650 ps t 8 pciclk cycle-cycle clock jitter measured at 1.5v 500 ps t 8 usbclk, ioclk cycle-cycle clock jitter measured at 1.5v 1.3 ns t 9 cpuclk, pciclk, sdram power-up time cpu, pci, and sdram clock stabili- zation from power-up 3 ms t 10 cpu, pci, sdram frequency slew rate rate of change of frequency 2 mhz/ ms notes: 9. all parameters specified with loaded outputs. 10. over the operating range unless otherwise specified. 11. parameters specified with: v ddcpu = 2.5v, v ddq2 = 2.5v, v ddq3 = 3.3v. 12. duty cycle is measured at 1.5v when v dd = 3.3v. when v ddcpu = 2.5v, cpuclk duty cycle is measured at 1.25v.
cy2277a rev 1.0, november 25, 2006 page 10 of 18 switching characteristics (-1m, -7m, -12m) [9, 10, 11] parameter output description test conditions min. typ. max. unit t 1 cpuclk sdram usbclk ref [0,1] ioapic output duty cycle [12] t 1 = t 1a t 1b 45 50 55 % t 1 pci output duty cycle [12] t 1 = t 1a t 1b 45 50 55 % t 2 cpuclk, ioapic cpu and ioapic clock rising and falling edge rate between 0.4v and 2.0v, v ddcpu = 2.5v cpu clocks at 66.66 mhz 0.60 4.0 v/ns t 2 pci pci clock rising and falling edge rate between 0.4v and 2.0v, v ddcpu = 2.5v 0.65 4.0 v/ns t 2 usbclk, ref0 usb, ref0 clock rising and falling edge rate between 0.4v and 2.4v 0.65 4.0 v/ns t 2 sdram sdram rising and falling edge rate between 0.4v and 2.4v sdram clocks at 66.66 mhz 0.70 4.0 v/ns t 2 ref1 ref1 rising and falling edge rate between 0.4v and 2.4v 0.5 2.0 v/ns t 3 cpuclk cpu clock rise time between 0.4v and 2.0v, v ddcpu = 2.5v 0.4 2.4 ns t 3 usbclk usb clock rise time between 0.4v and 2.0v 2.5 ns t 4 cpuclk cpu clock fall time between 2.0v and 0.4v, v ddcpu = 2.5v 0.4 2.4 ns t 4 usbclk usb clock fall time between 2.0v and 0.4v 2.5 ns t 5 cpuclk cpu-cpu clock skew measured at 1.25v, v ddcpu = 2.5v 100 250 ps t 5 pciclk pci-pci clock skew measured at 1.5v 400 ps t 5 sdram sdram-sdram clock skew measured at 1.5v 300 ps t 6 cpuclk, pciclk cpu-pci clock skew -1m, -12m measured at 1.25v fo r 2.5v clocks, and at 1.5v for 3.3v clocks 1.0 2.0 6.0 ns t 6 cpuclk, pciclk cpu-pci clock skew -7m measured at 1.25v fo r 2.5v clocks, and at 1.5v for 3.3v clocks 750 ps t 7 cpuclk, sdram cpu-sdram clock skew measured at 1.25v fo r 2.5v clocks, and at 1.5v for 3.3v clocks, v ddcpu = 2.5v 600 ps t 8 cpuclk cycle-cycle clock jitter measured at 1.25v for 2.5v clocks 525 ps t 8 sdram cycle-cycle clock jitter measured at 1.5v 600 ps t 8 pciclk cycle-cycle clock jitter measured at 1.5v 400 ps t 8 usbclk, ioclk cycle-cycle clock jitter measured at 1.5v 900 ps t 9 cpuclk, pciclk, sdram power-up time cpu, pci, and sdram clock stabili- zation from power-up 3 ms t 10 cpu, pci, sdram frequency slew rate rate of change of frequency 2 mhz/ ms
cy2277a rev 1.0, november 25, 2006 page 11 of 18 switching characteristics (-12) [9, 10, 11] parameter output description test conditions min. typ. max. unit t 1 all clocks output duty cycle [12] t 1 = t 1a t 1b 45 50 55 % t 2 cpuclk, ioapic cpu and ioapic clock rising and falling edge rate between 0.6v and 1.8v, v ddcpu = 2.5v between 0.4v and 2.4v, v ddcpu = 3.3v cpu clocks at 66.6 mhz 1.0 1.0 4.0 4.0 v/ns t 2 pci pci clock rising and falling edge rate between 0.4v and 2.4v, v ddcpu = 3.3v 1.0 4.0 v/ns t 2 ref0 ref0 clock rising and falling edge rate between 0.8v and 2.4v, v ddcpu = 3.3v 1.0 4.0 v/ns t 2 sdram sdram rising and falling edge rate between 0.5v and 2.0v sdram clocks at 66.6 mhz 1.5 4.0 v/ns t 2 ref1 usbclk ioclk ref1, usb and io rising and falling edge rate between 0.4v and 2.4v 0.5 2.0 v/ns t 3 cpuclk cpu clock rise time between 0.4v and 2.0v, v ddcpu = 2.5v between 0.4v and 2.4v, v ddcpu = 3.3v 0.4 0.4 2.0 2.0 ns t 3 usbclk, ioclk usb clock and i/o clock rise time between 0.4v and 2.4v 1.0 4.0 ns t 4 cpuclk cpu clock fall time between 2.0v and 0.4v, v ddcpu = 2.5v between 2.4v and 0.4v, v ddcpu = 3.3v 0.4 0.4 2.0 2.0 ns t 4 usbclk, ioclk usb clock and i/o clock fall time between 2.4v and 0.4v 1.0 4.0 ns t 5 cpuclk cpu-cpu clock skew measured at 1.25v, v ddcpu = 2.5v 100 250 ps t 6 cpuclk, pciclk cpu-pci clock skew (-12) measured at 1.25v fo r 2.5v clocks, and at 1.5v for 3.3v clocks 1.0 4.0 ns t 7 cpuclk, sdram cpu-sdram clock skew measured at 1.25v fo r 2.5v clocks, and at 1.5v for 3.3v clocks, v ddcpu = 2.5v 500 ps t 8 cpuclk cycle-cycle clock jitter measured at 1.25v for 2.5v clocks and at 1.5v for 3.3v clocks 250 ps t 8 pciclk cycle-cycle clock jitter measured at 1.5v 500 ps t 9 cpuclk, pciclk, sdram power-up time cpu, pci, and sdram clock stabili- zation from power-up 3 ms t 10 cpu, pci, sdram frequency slew rate rate of change of frequency 2 mhz/ ms
cy2277a rev 1.0, november 25, 2006 page 12 of 18 switching characteristics (-12i) [9, 10, 11] parameter output description test conditions min. typ. max. unit t 1 all clocks output duty cycle [12] t 1 = t 1a t 1b 45 50 55 % t 2 cpuclk, ioapic cpu and ioapic clock rising and falling edge rate between 0.6v and 1.8v, v ddcpu = 2.5v between 0.4v and 2.4v, v ddcpu = 3.3v cpu clocks at 66.6 mhz 1.0 .8 4.0 4.0 v/ns t 2 pci pci clock rising and falling edge rate between 0.4v and 2.4v, v ddcpu = 3.3v .9 4.0 v/ns t 2 ref0 ref0 clock rising and falling edge rate between 0.8v and 2.4v, v ddcpu = 3.3v 1.0 4.0 v/ns t 2 sdram sdram rising and falling edge rate between 0.5v and 2.0v sdram clocks at 66.6 mhz 1 4.0 v/ns t 2 ref1 usbclk ioclk ref1, usb and io rising and falling edge rate between 0.4v and 2.4v 0.5 2.0 v/ns t 3 cpuclk cpu clock rise time between 0.4v and 2.0v, v ddcpu = 2.5v between 0.4v and 2.4v, v ddcpu = 3.3v 0.4 0.4 3.0 2.0 ns t 3 usbclk, ioclk usb clock and i/o clock rise time between 0.4v and 2.4v 1.0 4.0 ns t 4 cpuclk cpu clock fall time between 2.0v and 0.4v, v ddcpu = 2.5v between 2.4v and 0.4v, v ddcpu = 3.3v 0.4 0.4 3.0 2.0 ns t 4 usbclk, ioclk usb clock and i/o clock fall time between 2.4v and 0.4v 1.0 4.0 ns t 5 cpuclk cpu-cpu clock skew measured at 1.25v, v ddcpu = 2.5v 100 250 ps t 6 cpuclk, pciclk cpu-pci clock skew (-12) measured at 1.25v fo r 2.5v clocks, and at 1.5v for 3.3v clocks 1.0 4.0 ns t 7 cpuclk, sdram cpu-sdram clock skew measured at 1.25v fo r 2.5v clocks, and at 1.5v for 3.3v clocks, v ddcpu = 2.5v 625 ps t 8 cpuclk cycle-cycle clock jitter measured at 1.25v for 2.5v clocks and at 1.5v for 3.3v clocks, v ddcpu =2.5v 350 ps t 8 pciclk cycle-cycle clock jitter measured at 1.5v 500 ps t 9 cpuclk, pciclk, sdram power-up time cpu, pci, and sdram clock stabili- zation from power-up 3 ms t 10 cpu, pci, sdram frequency slew rate rate of change of frequency 2 mhz/ ms
cy2277a rev 1.0, november 25, 2006 page 13 of 18 timing requirement for the smbus parameter description min. max. unit t 10 sclk clock frequency 0 100 khz t 11 time the bus must be free before a new transmission can start 4.7 s t 12 hold time start condition. after this period the first clock pulse is generated. 4 s t 13 the low period of the clock. 4.7 s t 14 the high period of the clock. 4 s t 15 setup time for start condit ion. (only relevant for a repeated start condition.) 4.7 s t 16 hold time data for cbus compatible masters. for smbus devices 5 0 s t 17 data input set-up time 250 ns t 18 rise time of both sdata and sclk inputs 1 s t 19 fall time of both sdata and sclk inputs 300 ns t 20 set-up time for stop condition 4.0 s switching waveforms duty cycle timing t 1a t 1b cpuclk outputs high/low time output v dd 0v t 1c t 1d all outputs rise/fall time output t 2 t 3 v dd 0v t 2 t 4
cy2277a rev 1.0, november 25, 2006 page 14 of 18 notes: 13. cpuclk on and cpuclk off latency is 2 or 3 cpuclk cycles. 14. cpu_stop may be applied asynchronously. it is synchronized internally. switching waveforms (continued) cpu-cpu clock skew t 5 clk clk cpu-sdram clock skew t 7 cpuclk sdram cpu-pci clock skew cpuclk t 6 pciclk cpu_stop cpuclk (internal) pciclk (internal) pciclk (free-running) cpu_stop cpuclk (external) [13, 14]
cy2277a rev 1.0, november 25, 2006 page 15 of 18 notes: 15. pciclk on and pciclk off latency is 1 rising edge of the external pciclk. 16. pci_stop may be applied asynchronously. it is synchronized internally. switching waveforms (continued) pci_stop cpuclk (internal) pciclk (internal) pciclk pci_stop pciclk (external) (free-running) [15, 16] pwr_down cpuclk (internal) pciclk (internal) pwr_dwn# pciclk cpuclk (external) (external) vco crystal shaded section on the vco and crystal waveforms indicates that the vco and crystal oscillator are active, and there is a valid clock. timing requiremen ts for the smbus sda scl t 11 t 12 t 13 t 14 t 15 t 17 t 18 t 19 t 20 t 16 t 12
cy2277a rev 1.0, november 25, 2006 page 16 of 18 application information clock traces must be terminated with either series or parallel termination, as is normally done. application circuit summary ? a parallel-resonant crystal should be used as the refer ence to the clock generator. the operating frequency and c load of this crystal should be as specified in the data sheet. optional trimming capacitors may be needed if a crystal with a different c load is used. footprints can be laid out for flexibility. ? surface mount, low-esr, ceramic capacitors should be used for filtering. typically, these ca pacitors have a value of 0.1 f. in some cases, smaller valu e capacitors may be required. ? the value of the series terminating resistor satisfies the following equation, where r trace is the loaded characteristic impedance of the trace, r out is the output impedance of the clock genera tor (specified in the data sheet), and r series is the series terminating resistor. r series > r trace ? r out ? footprints must be laid out for optional emi-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. typical values of these capacitors range from 4.7 pf to 22 pf. ? a ferrite bead may be used to isolate the board v dd from the clock generator v dd island. ensure that the ferrite bead offers greater than 50 impedance at the clock frequency, under loaded dc condi tions. please refer to the application note ?layout and termination techniques for cypress clock generators? for more details. ? if a ferrite bead is used, a 10 f? 22 f tantalum bypass capacitor should be placed close to the ferrite bead. this capacitor prevents power supply droop during current surges.
cy2277a rev 1.0, november 25, 2006 page 17 of 18 test circuit 3 7 10 0.1 f 15 17 v ddq3 c load outputs 37 28 43 0.1 f note: all capacitors should be placed as close to each pin as possible. 0.1 f 21 24 34 31 46 0.1 f 0.1 f 0.1 f v ddq2 0.1 f v ddcpu 40 25 0.1 f 48 0.1 f ordering information ordering code package name package type operating range CY2277APVC-1 o48 48-pin ssop commercial cy2277apac-1m z48 48-pin tssop commercial cy2277apvc-3 o48 48-pin ssop commercial cy2277apac-7m z48 48-pin tssop commercial CY2277APVC-12 o48 48-pin ssop commercial cy2277apac-12m z48 48-pin tssop commercial cy2277apvi-12 o48 48-pin ssop industrial
rev 1.0, november 25, 2006 page 18 of 18 cy2277a while sli has reviewed all information herein for accuracy and re liability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it inte nded for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear in c., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. package drawing and dimension 48-lead shrunk small outline package o48 48-lead thin shrunk small outline package, type ii (6 mm x 12 mm) z48

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